AlpinumDV 2.0.0: from a spec to a self-verified UVM testbench, in a single command
Design verification is where silicon schedules go to slip. Before an engineer runs a single check, they spend days, often weeks, building the UVM environment by hand: wiring agents and sequencers, hand-coding a reference model, assembling a coverage plan, and grinding through the compile errors that stand between a fresh testbench and its first simulation. It is skilled, expensive work, and almost none of it is the actual verification.
AlpinumDV 2.0.0 removes that entire front end. You give it the design specification, and the RTL if you have it, and it returns a complete, compiled, self-debugged UVM 1.2 testbench together with an honest pass/fail verdict. One command in; a running, verified environment out.
How it works, stage by stage
AlpinumDV runs a six-stage pipeline, and every stage is transparent as it writes out the plan, the reference, and the verdict so nothing is a black box
Understand
It parses the RTL interface, reads the full specification folder, and classifies the design into a complexity tier (combinational, memory-backed, CSR/register block, bus bridge, or CPU) so the strategy fits the design instead of forcing one template onto everything.
Plan
It generates a scalable test plan (exported as JSON, text, and spreadsheet), a functional coverage model, and SystemVerilog assertions derived from the spec.
Reference model
If you supply a golden reference, it uses it. If you don't, it writes one directly from the specification, translating the design's intended behavior into a behavioral model, then validating and refining that model against corner vectors before it is trusted.
Generate
It builds the full UVM environment in a clean UVC folder layout (interface, agent, driver, monitor, scoreboard, coverage, sequences, tests).
Simulate and self-debug
It compiles, runs, and, when the simulator complains, reads its own logs and fixes its own testbench errors automatically, iterating until it compiles clean and runs.
Close coverage
An AI coverage oracle identifies the bins that stayed uncovered and generates directed tests aimed precisely at them, pushing toward a 90% functional coverage target.
An honest verdict, this is the part that matters
Automated verification is only useful if you can trust what it tells you. AlpinumDV distinguishes three outcomes, and never conflates them: a genuine PASS (every transaction matched, no assertion failures); an RTL bug, which is a real defect caught against a trusted reference; and a reference-unverified result, where a mismatch is flagged as a limitation of an AI-written reference rather than blamed on the design. Coverage is reported as a quality number, never as a pass/fail gate. The result is a tool that finds real bugs, confirms clean designs cleanly, and, critically, does not cry wolf.
What version 2.0 adds
- AI reference models that read like hand-written ones, translating complex RTL block by block rather than guessing at behavior.
- Self-correcting references that learn from real simulation mismatches and refine before delivering a verdict.
- Machine-code stimulus for processors: A self-contained RV32I toolchain (assembler, encoder, program generator, no external compiler required) that runs real programs through a CPU. On our RISC-V core this lifts functional coverage from an idle ~25% (fetching NOPs) to 61%, fully autonomously.
- Model-agnostic operation: AlpinumDV runs on any OpenAI-compatible endpoint, its default engine, Mistral, or OpenAI, selected purely by configuration.
Proven at scale
In our most recent benchmark run, AlpinumDV processed a 14-design suite in about three hours with zero hand-written testbenches, from simple combinational blocks up to a serial peripheral and a RISC-V processor. It verified every clean design correctly and correctly reported the planted defects, with no false passes and no false bug reports on good designs.
Headline Scorecard (Golden-Reference Mode)
| Metric | Result | Meaning |
|---|---|---|
| Real designs clean | 12 / 12 | Every transaction matched; zero assertion failures |
| Bug fixtures caught | 2 / 2 | Planted RTL defects correctly reported |
| Verdict accuracy | 100% | No false passes, no false bugs on good designs |
| Hand-written testbenches | 0 | Whole suite generated automatically (~3 hours) |
Per-Design Results
| Design | Class | Scoreboard | Coverage | Verdict |
|---|---|---|---|---|
| adder | Combinational | 207 / 207 | 100% | ✓ PASS |
| adder32 | Combinational | 229 / 229 | 100% | ✓ PASS |
| alu | Combinational | 3,576 / 3,576 | 99% | ✓ PASS |
| alu_noref | Combinational | 2,749 / 2,749 | 100% | ✓ PASS |
| sim_only_alu | Combinational | 3,886 / 3,886 | 100% | ✓ PASS |
| counter | Sequential | 1,937 / 1,937 | 100% | ✓ PASS |
| single_port_ram | Memory | 414 / 414 | 100% | ✓ PASS |
| dual_port_ram | Memory | 470 / 470 | 100% | ✓ PASS |
| fifo | Memory / CDC | 4,128 / 4,128 | 100% | ✓ PASS |
| apb_slave | Bus protocol | 2,741 / 2,741 | 96% | ✓ PASS |
| spi | Serial | 10,849 / 10,849 | 97% | ✓ PASS |
| RISCV_CPU | CPU / ISA | 272 / 272 | 58% | ✓ PASS |
| adder_bugs | Bug injected | Defect caught | 100% | ● RTL BUG |
| counter_bugs | Bug injected | Defect caught | 100% | ● RTL BUG |
Every real design verified cleanly against its golden reference, and both
bug fixtures had their planted defects correctly reported as the tool
caught every injected bug and raised no false alarms on the good designs.
AlpinumDV 2.0.0 is available now under our license agreement, with an online version so you can try it without installing anything.
Access AlpinumDV 2.0.0
AlpinumDV 2.0.0 is available under the Alpinum licence agreement. An online version is also available, allowing users to try the tool without installing it locally. Contact Alpinum to discuss licence access and deployment options, or use the Online Submission Portal to explore the available AlpinumDV workflow and demonstrations.
